1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a semiconductor memory device having a dynamic random access memory (DRAM) and a static random access memory (SRAM) formed on the same semiconductor chip, and to a method of driving the semiconductor memory device. More particularly, the invention relates to a semiconductor memory device containing cache with a main memory and a cache memory formed on the same semiconductor chip, and to a method of driving the semiconductor memory device.
2. Description of the Background Art
With progress of semiconductor technology, a central processing unit (CPU) has become operable at high speed and so has a DRAM. However, a DRAM cannot follow the development in the speed of CPU and the difference in operating speed therebetween has increased. This is bottle-neck in improvement of data processing speed of computer systems.
In a large-scale system such as a mainframe, a high-speed cache memory is interposed between a main memory and a CPU to compensate for the operating speed of the main memory, thereby to improve performance without a significant increase in cost.
For a small-scale system, a construction has been proposed and put to practical use, in which a cache memory is formed on the same semiconductor chip as that on which a DRAM is formed, to realize equivalently a high-speed operation of the main memory. In such DRAM containing cache, data transfer between an SRAM acting as cache memory and a DRAM acting as main memory is effected at high speed by using an internal data bus having a large bit width.
FIG. 1 shows a conceptional construction of a system employing a conventional DRAM containing cache.
Referring to FIG. 1, the processing system comprises a microprocessor 100 for carrying out various processes according to predetermined programs, a cache controller 110 for controlling operation of the cache memory, a tag 120 operable in response to an address from outside of the cache for determining a cache hit/miss and designating a corresponding "way", a DRAM controller 130 for controlling operation of a DRAM section, and a DRAM 200 containing cache memory (cache DRAM).
The cache DRAM 200 includes a DRAM section 210 having, for example, a 1M bit storage capacity, and an SRAM section 220 having, for example, an 8K bit storage capacity. The DRAM section 210 includes 4 plates of 256K bit DRAM, each DRAM plate being divided into 64 groups each having an 8-bit width. The SRAM section 220 includes 2 plates of 2K bit SRAM, each SRAM plate being divided into 64 blocks each having a 32-bit (8.times.4) size. Each block of the SRAM is further divided into four 8-bit ways. This construction provides a four-way set associative system. The input/output data width is 4 bits (DQ1-DQ4).
Data transfer between DRAM section 210 and SRAM section 220 is performed in a block through an internal data bus 230 having a 32-bit width.
The microprocessor 100 transfers 4-bit data DQ1-DQ4, outputs 18-bit addresses A0-A17, and transmits necessary control signals to the DRAM controller 130 and cache controller 110.
Though not expressly shown, the tag 120 includes a tag memory for storing addresses (tag address A0-A8 and set address A9-A14) for data stored in the SRAM section 220, a comparator for comparing the tag addresses stored in the tag memory and an address received from the microprocessor 100, and a tag replacement logic processor for generating a way address designating a region of the SRAM section 220 for which data rewriting is to be carried out in accordance with a result of comparison in the comparator.
The cache controller 110 is operable in response to a cache hit/miss indicating signal from the tag 120 for generating a signal BT instructing data transfer between SRAM section 220 and DRAM section 210.
The DRAM controller 130 generates a row address strobe signal RAS and a column address strobe signal CAS for operating the DRAM section 210 on a cache miss. A data reading operation of this cache DRAM will be described briefly in the following.
The SRAM section 220 has a four-way, 64-set construction. One set corresponds to one block in the DRAM section 210. Access is made to this cache DRAM according to the 18-bit address signals A0-A17. Fifteen bits in the 18-bit address A0-A17 are applied also to the tag 120. The tag address and set address (address A0-A14) applied to the tag 120 are compared with the addresses stored therein, and cache hit/miss is determined on the result of the comparison.
In parallel with the cache hit/miss determination at the tag 120, access is made to the SRAM section 220 in the cache DRAM 200. The address signals A9-A14 designate one of the 64 sets in the SRAM section 220, and the address signals A15-A17 designate which of the eight columns (One set has 8 bits.) in the designated set is addressed. The 16 bits present on the designated column (4 bits per way) are transmitted to a stage just front of an output.
When an address of data stored in the SRAM section (cache memory) 220 coincides with an address stored in the tag 120, the tag 120 further decodes this address and outputs a 2-bit way address WA0, WA1. As a result, one way is selected from the four ways read simultaneously, and 4-bit data DQ1-DQ4 is read out in parallel.
Data is read from the DRAM section 210 at a cache miss when the external address does not coincide with every address stored in the tag 120. The data reading is carried out in a way similar to access to an ordinary DRAM. That is, data is read by using the address signals A0-A8 as a row address signal and the address signals A9-A17 as a column address signal, and in response to the control signals RAS and CAS from the DRAM controller 130.
At a cache miss, the block (32 bits: corresponding to one way) in the DRAM section 210 including the 4 bits to which access has been made is transferred to the SRAM section 220 through the internal data bus 230. Timing of this transfer is controlled by the control signal BT from the cache controller 110. The replacement logic processor included in the tag 120 determines to which of the ways in the SRAM section 220 the transferred block data should be written. That is, the tag 120 generates the way address WA0, WA1 for selecting a way in the SRAM section 220.
In rewriting of data in the SRAM section (cache memory) 220, data of corresponding memory cells in the DRAM section 210 are also rewritten simultaneously (i.e. a write-through mode). Data writing to the DRAM section 210 is carried out in the same way as access to an ordinary DRAM. In this case, however, whether the written data is transferred also to the SRAM section 220 or not is optionally determined, and the choice is made through the transfer control signal BT.
FIG. 2 shows a specific construction of the cache DRAM. This cache RAM construction shows circuitry relating to data reading, which is shown in 1989 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, pages 43-44, for example.
Referring to FIG. 2, the DRAM section 210 includes a DRAM cell array 211 having a capacity of 1M (2.sup.20) bits, a row decoder 212 for selecting one row in the DRAM cell array 211 in response to an externally applied row address A0-A8, a column decoder 213 for selecting 32 columns in the DRAM cell array 211 in response to 6-bit column address A9-A14 in an externally applied column address A9-A17, a DRAM sense amplifier 214 for detecting and amplifying data of memory cells in one row selected by the row decoder 212, an I/O gate 215 for connecting the selected columns to the internal data bus 230 in response to output of the column decoder 213, and a 1/8 decoder 231 for selecting four data lines from the 32-bit data lines in the internal data bus 230 in response to 3-bit column address A15-A17 in the externally applied column address.
The SRAM section 220 includes a SRAM cell array 221 having an 8K bit storage capacity, a set decoder 222 for receiving 6-bit set address A9-A14 among en externally applied cache address (the column address) A9-A17, and selecting one set or one row from the 64 sets in the SRAM cell array 221, a SRAM column decoder 213 for selecting 16 columns from the selected set in response to 3-bit address A15-A17 among the cache address A9-A17, an SRAM sense amplifier 294 for detecting and amplifying the data in the columns selected by the SRAM column decoder 213, a first way decoder 216 for selecting 4-bit data of one way from the 16-bit data of the four ways in response to an externally applied way address WA0, WA1, and a second way decoder 294 for selecting a way in the SRAM cell array 221 to be written with the 32-bit data transferred from the DRAM section 210 in response to the way address WA0, WA1 at a cache miss, and writing the 32-bit data to a selected way.
A hit/miss buffer 232 is provided for selecting either the DRAM section 210 or the SRAM section 220 in response to a cache hit/miss indicating signal H/M. This hit/miss buffer 232 not only buffers the cache hit/miss indicating signal H/M to generate a control signal for controlling operation of the first way decoder 216, but also maintains the output DQ0 to DQ4 at a high impedance until DRAM data is read and transmitted at a cache miss. Further, the hit/miss buffer 232 selects either the 1/8 decoder or the first way decoder in response to the cache hit/miss indicating signal H/M. Operations will be described next.
(i) At hit read
When a cache address A9-A17 is applied to the SRAM section 220, the SRAM section 220 is activated regardless of a cache hit/miss. The set decoder 222 decodes the 6-bit set address A9-A14 in the cache address A9-A17, and selects one set in the SRAM section 220. Since the selected set includes four ways and each way has 8 bits, 32-bit memory cells in total are selected simultaneously. Subsequently, the column decoder 223 decodes the 3-bit column address A15-A17, and selects one of the eight rows in one set. As a result, 16-bit memory cells in total are selected, with 4 bits selected from each way. The data of the 16-bit memory cells are amplified by the sense amplifier 295 and are then transmitted to the first way decoder 216.
At a time of cache hit, the way address WA0, WA1 is applied to the first way decoder 216. Based on the way address WA0, WA1, the first way decoder 216 selects one of the four ways and applies 4-bit data of the selected way to the hit/miss buffer 232. The hit/miss buffer 232, in response to a hit signal H, selects the 4-bit data from the first way decoder 216, and outputs the data as output data DQ1-DQ4.
(ii) At a hit write
When the column address A0-A8 and cache/column address A9-A17 are applied to the cache DRAM, the DRAM section 210 and SRAM section 220 are activated. In response to a hit indicating signal H and a write instruction signal, the hit/miss buffer 232 applies external data DQ1-DQ4 to the first way decoder 216 and 1/8 decoder 231. In the SRAM section 220, the first way decoder 216 selects four bus lines in the 16-bit wide data bus in response to the way address WA0, WA1, and transmits the 4-bit data to the SRAM cell array 221 through the sense amplifier 295. At a data writing, the sense amplifier 295 does not operate and the data for writing is simply transmitted to the SRAM cell array 221. The set decoder 222 selects one set in the SRAM cell array, while the SRAM column decoder 223 selects four columns in the selected set. At this time, the second way decoder 294 also operates to select and activate only one of the four ways. As a result, 4-bit data is written to the columns corresponding to the selected way.
In parallel with the operation for the SRAM section 220, data is written to the DRAM section 210. Though a data writing path to the DRAM section 210 is not expressly shown, the 1/8 decoder 231 selects four bus lines in the 32-bit internal data bus 230, and the data DQ1-DQ4 for writing is transmitted through the four selected bus lines. The remaining bus lines are maintained at a high impedance.
At a time of the data transfer for writing, 4-bit memory cells are already selected in the DRAM section 210 by the row address A0-A8 and column address A9-A17. The DRAM decoders 212 and 213 select 32 bits simultaneously, and the data for writing appears on only 4 bits among the 32 bits. The remaining data bus lines are at the high impedance, and the latching function of the DRAM sense amplifier 214 prevents adverse effect on the non-selected bits.
The operation for writing data to the SRAM cell array 221 and writing data to the corresponding memory cells (bits) in the DRAM cell array 211 at the same time is called a write-through mode.
(iii) At a miss read
A reading operation in the SRAM section 220 based on the cache address A9-A17 is the same as for hit read until the way address WA0, WA1 is applied to the first way decoder 216.
At a cache miss, the way address WA0, WA1 is not applied to the first way decoder 216 and the latter remains inoperative.
At this time, the external control signals RAS and CAS cause the DRAM section 210 active to take the row and column addresses A0-A8 and A9-A17 therein. The DRAM row decoder 212 and DRAM column decoder 213 decode the address A0-A17, and 32-bit data (one block) including the addressed 4-bit data are read out for transmission to the internal data bus 230.
The 1/8 decoder 231, in response to the 3-bit address A15-A17, selects 4 bits from the 32-bit them to the hit/miss buffer 232. In response to a cache miss signal M, the hit/miss buffer 232 selects the data received from the 1/8 decoder 231, and sets the output data DQ1-DQ4, which have been in the high impedance, to potential levels corresponding to the received data.
In parallel with this data reading, the way address WA0, WA1 is applied to the second way decoder 4 at a cache miss, after a fall of the signal RAS, i.e. after an operation of the DRAM section 210. The second way decoder 294 also receives the 32-bit data from the internal data bus 230. The second way decoder 294 is activated by the transfer control signal BT to decode the way address WA0, WA1 and select a way. 32-bit data transferred from the DRAM section 210 is written to one of the four ways selected by the set decoder 222 and SRAM column decoder 223. As a result, data in the corresponding memory cells in the SRAM cell array are renewed.
(iv) At a miss write
The cache miss signal M is applied along with a write instruction signal (not shown) to the cache DRAM. At a cache miss, the signals RAS and CAS activate the DRAM section 210 to select memory cells in the DRAM section 210 in accordance with the row address A0-A8 and column address A9-A17. The hit/miss buffer 232 does not select the SRAM section 220 but selects the DRAM section 210, or selects only the 1/8 decoder 231. As a result, input data. DQ1-DQ4 is written to the 4-bit DRAM memory cells corresponding to the external address A0-A17.
At this time, the SRAM section 220 engages only in a memory cell selecting operation by means of the set decoder 222 and SRAM column decoder 223. At the miss write, whether the 4-bit data written to the DRAM section 210 is to be transferred to the SRAM section 220 or not is optional, and the choice is made through the transfer control signal BT.
The basic concept of the conventional cache DRAM is such that a part of the data in the DRAM cell array 211 are stored in the SRAM cell array 221 and, upon an access request from an external processor, (i) the SRAM cell array 221 is accessed for data reading or writing if corresponding data is stored in the SRAM cell array 221, and (ii) if corresponding data is not found in the SRAM cell array 221, access is made to the DRAM cell array 211 in response to the cache miss signal for reading or writing the data to/from the DRAM cell array 211.
Generally, access time of the SRAM is 10 to 20 ns which is faster than that of the DRAM. However, the memory cells in the SRAM have a flip-flop type construction, and at least four transistors are required for each cell. The SRAM is inferior in the degree of integration and cost per bit to the DRAM which requires one transistor for each cell. However, the DRAM generally has an access time of 50 to 100 ns, which is slower than the SRAM.
The cache DRAM has been devised to compensate for the drawbacks of the DRAM and SRAM while retaining the advantages of the two. According to this construction, an average access time may virtually be reduced to the same level as that of the SRAM if the data to which access is requested from an external processor is present in the SRAM section with a very high probability. In this way, a large-capacity, high-speed memory device may be realized which has a degree of integration comparable to the DRAM and an access time comparable to the SRAM.
However, the conventional cache DRAM requires a tag that compares the address of the memory cell requested by an external processor and the address of each data block stored in the SRAM section, and determines from the result of this comparison whether or not the requested data (or data block) is present in the SRAM section. This poses a problem of enlarging the device scale.
There is a mode called a write-back mode which is an improvement in system efficiency to the write-through mode noted hereinbefore which writes data to the DRAM section each time the data is written to the SRAM section. According to the write-back mode as employed in a processing system having main memory and cache memory, generally, data are written only to the cache memory and the newly written data are transferred in a batch to the main memory later on. Since the main memory is slower than the cache memory and requires a long time for data writing, the write-back mode for writing data in a batch from the cache memory to the main memory provides a shorter total cycle time than the write-through mode does.
However, the write-back mode requires a buffer for storing the addresses for the cache memory to which data have been rewritten, and a control circuit for maintaining consistency in operation (writing timing, operating speed and others) between cache memory and main memory. In the cache DRAM, the DRAM corresponds to the main memory in an ordinary system, and the SRAM to the cache memory. To effectuate the write-back mode in the conventional cache DRAM, therefore, it is necessary to add, as external components, a buffer for storing the addresses of the memory cells in the SRAM section having the data renewed, and a control circuit for controlling the batch transfer of the renewed data from the SRAM section to the DRAM section. This results in an enlarged device and complicated setting of the control timing. Thus, it is difficult to realize the write-back mode in the conventional cache DRAM by means of a simple construction.
Further, the tag must include, in addition to the tag memory for storing the addresses of data stored in the SRAM section, the replacement logic processor for selecting a way to which a new data is written at a cache miss, and the comparator for determining a cache hit/miss. Consequently, it is difficult to realize a tag with a simple construction.